This invention relates to phase selection of a clock signal and, in particular, to apparatus and methods for producing different phases of a clock signal and for selecting certain of these clock signals for operating a system with reduced jitter.
In many systems, such as in digital clock recovery systems and frequency synthesis systems, clocking (or "timing") signals are generated for "retiming" incoming data and/or performing needed timing/clocking operations. By way of example, in a digital clock recovery system, a basic clock signal of given frequency is generated together with a number of different clock signals of like frequency but with different phases, e.g., the different clock signals may be generated by applying the basic clock signal to analog and/or digital delay networks. Then, in the course of operating the system different ones of the clock signals are compared to the phase and frequency of an incoming data stream and certain ones of the clock signals are selectively switched into use by the system for performing data recovery. However, when a clock signal of one phase is switched into the system to replace a clock signal of a different phase there is a fixed, discrete, jump in the phase (timing) of the clock signal being used, even though the frequency is the same. The "jumping" back and forth in the phase of the clocking signal is problematic in that it introduces a certain discrete amount of jitter in the clocking/timing signals generated by the system and used therein.
The nature of the problem present in prior art systems may be better explained with reference to the prior art clock recovery circuit shown in of FIG. 1 which includes a clock generation system for producing a clock signal with a predetermined number of phases. The clock generation circuit includes a reference clock signal (fref) applied to the input of a voltage controlled delay line (VCDL) 12 which is shown to include 4 inverters (I1,I2, I3,I4) connected in cascade between an input terminal 11 to which is applied fref and an output terminal 13. The signal fref and the output of VCDL 12 are applied to a phase detector 14 which produces an output which controls a charge pump circuit 16 whose output is supplied to a filter 18 whose output voltage controls the delay in (and of) the stages of VCDL 12. Consequently each one of the inverters in VCDL 12 produces a differently phased clock (i.e., .phi.1, .phi.2, .phi.3, .phi.4) but with all the clock signals having the same frequency.
The four output clocks (.phi.1, .phi.2, .phi.3, .phi.4) of VCDL 12 are supplied to a multiplexer 20, which in response to a control signal (CTLS) selects one of the four VCDL generated clocks and couples it to the multiplexer output line 23. In a clock recovery system an incoming data signal stream (DATA) applied to the system is compared to the phase of the clock signal on line 23 to ascertain that the data being received by the system has a particular frequency and phase. The clock signal on line 23 is applied to one input of a phase detector 22 having another input 24 to which is applied the incoming data signal stream (DATA) whose frequency and phase is to be ascertained. If there is a difference in phase between the incoming DATA on line 24 and the clock signal on line 23 an error signal is generated which is applied to a control circuit 25 which then produces an output signal (CTLS) on line 21 to cause multiplexer 20 to switch and select a different phase (i.e., a different one of the four clock signals being outputted by VCDL 12) until there is a match between the frequency and phase of the clock signal and the frequency and phase of the incoming DATA. Note that the clock signal on line 23 and the incoming data signals are also applied to a data sampling flip-flop 26 at whose output is produced a "retimed" data signal which is then fed to an electronic system for processing. The clock signal on line 23 thus functions as a sampling clock which may also be termed the data "recovery" clock. Theoretically, to best sample the true value of incoming data bits, the sampling clock should sample the incoming data bits midway between the rising and falling edges of a data bit. When the sampling clock is subject to jitter the sampling clock may occur at or near the (rising or falling) edges of the incoming data bits resulting in a high number of erroneous sampling of the incoming data.
Thus, a problem with the circuit of FIG. 1 is that when the control signal CTLS activates the multiplexer to select a different clock signal, the clock "recovery" signal at the output of the multiplexer, which is applied to line 23, switches from one phase of the clocking signal to another phase of the clocking signal. This causes a discrete jump and resulting jitter, having a fixed minimum value, in the clocking and sampling signals supplied to the system and in the data to be processed by the system.